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3.8.6
Signal Compensation
The device includes internal OTP and signal processing to compensate for sensitivity error and offset error. This compensation
is necessary to achieve the specified parameters in Section 2.4 .
3.8.7
Output Scaling
The 20 bit digital output from the DSP is clipped and scaled to a 12-bit data word which spans the acceleration range of the
device. Figure 22 shows the method used to establish the output acceleration data word from the DSP output.
Over Range
Signal
Noise
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
12-Bit Data Word
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
Using Rounding
Figure 22. 12-Bit Output Scaling Diagram
3.8.8
Data Interpolation
The device includes 2 to 1 data interpolation to minimize the system sample jitter. Each result produced by the digital signal
processing chain is delayed one half of a sample time, and the interpolated value of successive samples is provided between
sample times. This operation is illustrated below.
Internal Sample Rate
S n-3
t s
S n-2
t s
S n-1
t s
S n
t
S n – 3 + S n – 2
S n – 2 + S n – 1
S n – 1 + S n
S n-3
-------------------------------
2
S n-2
-------------------------------
2
S n-1
------------------------
2
Output Sample Rate
t
SPI acceleration request occurring in this window receives interpolated sample
SPI acceleration request occurring in this window receives true sample.
Figure 23. Data Interpolation Timing
MMA655x
Sensor
34
Freescale Semiconductor, Inc.
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